1. Field of the Invention
The invention relates to techniques for verifying circuit layouts for semiconductor chips. More specifically, the invention relates to a method and an apparatus for identifying line-end features for lithography verification.
2. Related Art
As semiconductor integration densities continue to increase at an exponential rate, circuits are becoming increasingly larger, which makes it more computationally expensive to simulate the final printed image for a circuit layout. Consequently, such simulations are usually performed only for certain identified critical regions in the circuit based on the relative locations of specific features that are likely to cause problems, such as line ends.
Furthermore, because of increasing integration densities, feature sizes are becoming increasingly smaller, which leads to problems with etch bias effects and optical proximity effects, which can distort the final printed image of a circuit layout. In order to compensate for these effects, circuit layouts are typically modified through etch bias correction and optical proximity correction operations. Artifacts, such as serifs, which are generated by these correction operations, can cause difficulties in identifying line-end features.
Currently existing techniques for line-end detection suffer from low-precision when handling data with a high amount of noise, and from the difficulty in processing runs in directions such as 30 degrees and 45 degrees. These difficulties largely arise because the artifacts introduced by etch bias correction and optical proximity correction tend to generate noise, which obscures the line-end features.
Hence, what is needed is a method and an apparatus for identifying line-end features for lithography verification without the above-described problems.